1. Technical Field
The invention relates generally to circuits fabricated using a combination of bipolar and complementary metal oxide silicon transistors (hereinafter BICMOS), and more particularly to a BICMOS output circuit.
2. Background Art
BICMOS technology has gained increasing acceptance in the industry, because it combines the low power attributes of traditional CMOS designs with the high speed attributes of bipolar transistor technology. BICMOS is particularly applicable to static random access memories (SRAMs), especially those operating in the sub 10 ns access range, where bipolar devices are used to quickly drive sensed data off the chip and CMOS devices are used to provide low power memory cells.
In conventional push-pull BICMOS output drivers of the prior art, it is known to use CMOS devices to drive bipolar output devices coupled to high and low power supplies. A general concern that must be addressed in such circuits is how to provide a full voltage swing at the output (that is, an output voltage within 0.1 volts of a power supply potential) with fast rise/fall times (switching speeds).
This problem is discussed and illustrated in an article by Puri et al., "Non-Inverting BIFET Buffer Circuit," IBM Technical Disclosure Bulletin, Vol. 23, No. 2, July 1990 pp. 283-85. The circuit discussed in the article is illustrated in FIG. 1 (Prior Art). Transistors Q5 and Q6 are NPN bipolar transistors; the remaining transistors are FETs, wherein transistors Q2-Q4 are n-channel FETs (NFETs) and transistor Q1 is a P-channel FET (PFET). The output is driven by bipolars Q5 and Q6 in a "push-pull" configuration. That is, when the input voltage IN is low, Q5 turns on to "push" the output to VDD. When IN is high, Q6 turns on to "pull" the output to ground. However, since the base of Q6 is driven positive to pull the output low, Q6 could go into saturation since the base voltage becomes higher than the collector voltage as the output is pulled low. A simple solution to this problem is to couple the drain of FET Q3 to the output, such that the base of Q6 is connected to the collector of Q6 by FET Q3, such that Q6 will never go into saturation.
Most of the BICMOS art couples the source of the driver FET to the output, to limit the drive on the base of the bipolar as in the Puri et al. article. Examples include Puri et al., "Improved BIFET Circuit," IBM Technical Disclosure Bulletin, Vol. 33, No. 1A, June 1990 pp. 274-78; U.S. Pat. No. 4,616,146 (Lee et al.--Motorola); U.S. Pat. No. 4,649,295 (McLaughlin et al.--Motorola); U.S. Pat. No. 4,694,203 (Uragami et al.--Hitachi); U.S. Pat. No. 4,779,014 (Masuoka et al.--Toshiba); U.S. Pat. No. 4,845,385 (Ruth--Silicon Connections Corp.); U.S. Pat. No. 4,845,386 (Ueno--Toshiba); U.S. Pat. No. 4,849,658 (Iwamura et al.--Hitachi); U.S. Pat. No. 4,879,480 (Suzuki et al.--Hitachi); U.S. Pat. No. 4,890,018 (Fukushi et al.--Fujitsu); U.S. Pat. No. 4,933,574 (Lien et al.--Integrated Device Technology, Inc.); U.S. Pat. No. 4,970,414 (Ruth--Silicon Connections Corp.); U.S. Pat. No. 4,977,337 (Ohbayashi et al.--Mitsubishi); Japanese Application 63-4713 (Kanzawa et al--Hitachi); and Japanese Application 01-270412.
The prior art that clamps the base voltage to the output through the control FET reduces the voltage swing at the output. That is, in order to prevent saturation, the base voltage is reduced as the output (i.e. the collector voltage) drops, throughout the output drive cycle. Dropping the base voltage also reduces the transistor drive, such that the transistor conducts less current. As a result, the switching time at the output increases, and the collector voltage does not reach the full power supply potential.
Thus, in the prior art concern about saturation limited performance. That is, because base drive was reduced in order to keep the bipolar out of saturation these circuits provide less than a fast transition full voltage swing by approximately 1 Vbe (0.8 volts). As CMOS voltages are reduced due to device scaling, this reduction in voltage swing can eliminate BICMOS speed advantages over CMOS.
Accordingly, a need has developed in the art for a BICMOS driver that provides full voltage swings and fast switching times without consuming excessive power.